RTL Test Justification and Propagation Analysis for Modular Designs

Modular decomposition and functional abstraction are commonly employed to accommodate the growing size and complexity of modern designs. In the test domain, a divide & conquer type of approach is utilized, wherein test is locally generated at each module’s boundary and consequently translated to global design test. We present an RTL analysis methodology that identifies the test justification and propagation bottlenecks, facilitating a judicious DFT insertion process. We introduce two mechanisms for capturing, without reasoning on the complete functional space, data and control module behavior related to test translation. A traversal algorithm that identifies the test translation bottlenecks in the design is described. The algorithm is capable of handling cyclic behavior, reconvergence and variable bit-widths in an efficient manner. We demonstrate our scheme on representative examples, unveiling its potential of accurately identifying and consequently minimizing the reported controllability and observability bottlenecks of large, modular designs.